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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking talented Application Engineers dedicated for physical design in Cadence Korea. You will be responsible for the physical design implementation projects. The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes. The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development. 15+ experience with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues. Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R. Able to assume responsibility for a variety of technical tasks and to work independently Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs Self-motivated, able to work as a team player, and good English communication skills The candidate will work closely with RTL design team to ensure successful tapeouts. We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Lead Software Engineer to work with us in San Jose, California. At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and is also a Fortune 100 Best Companies to Work For . As a Lead Software Engineer, you will be part of the HSV Software team in the SVG group in San Jose, California. The HSV Software team builds AI-enabled software products that support emulation and prototyping platforms, helping customers accelerate design bring-up, debug, verification, and validation workflows. To understand more on what we do, you can visit https://www.cadence.com/en_US/home/tools/system-design-and-verification.html . Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world. Job Description: Design and develop AI-enabled software components for emulation and prototyping workflows, balancing reliability, maintainability, security, latency, cost, and integration with existing product architecture. Build LLM-based agents, RAG workflows, and automation services that improve design bring-up, verification, debug, and validation while recommending product enhancements beyond defect fixes. Apply secure and responsible AI practices, including data protection, access control, prompt-injection awareness, safe tool use, auditability, and careful handling of sensitive design data. Create and execute testing, evaluation, and observability workflows for assigned AI product areas, covering regression tests, retrieval quality, model-output review, tracing, and failure analysis. Serve as a technical resource for peers and less-experienced engineers, collaborating with internal partners, senior individual contributors, and managers to deliver high-quality AI-enabled software. Requirements: Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience; typically 4+ years with a Bachelor’s, 2+ years with a Master’s, or PhD-level preparation in related software development. Strong Python skills and software engineering fundamentals, including APIs, testing, debugging, maintainability, Unix/Linux environments, and distributed development workflows. Hands-on experience building AI-enabled applications, agentic workflows, or automation services using LLM APIs, open-source models, enterprise AI platforms, and orchestration tools such as LangGraph, LangChain, AutoGen, CrewAI, or similar frameworks. Understanding of modern RAG and agentic AI patterns, including retrieval, chunking, embeddings, vector or hybrid search, reranking, tool calling, workflow orchestration, human-in-the-loop review, and traceability. Ability to evaluate, secure, and debug AI product behavior using golden datasets, regression tests, hallucination checks, prompt and retrieval analysis, observability traces, quality metrics, and responsible AI practices. Nice to have: Experience developing software using version control systems and modern CI/CD practices. Experience with other programming languages such as C++, Tcl, or JavaScript/TypeScript. Knowledge or experience with design verification, emulation, prototyping, or hardware-assisted debug workflows. Knowledge or experience with EDA and VLSI design, including Verilog, SystemVerilog, or VHDL. Exposure to practical AI application security, such as prompt-injection awareness, safe tool integration, access control, input/output validation, or secure handling of design data. Additional Job Details: Employment category: Full-time. Employment term: 40 hours/week. Competitive benefits. Location: San Jose, California. About Cadence Design Systems: Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com. We’re doing work that matters. Help us solve what others can’t. The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Software Engineer II: R&D Hardware Verification to work with us in Belo Horizonte, Brazil. At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For . As a Software Engineer II: R&D Hardware Verification , you will be part of HSV in the SVG group in Belo Horizonte, Brazil. The HSV group works with Palladium , the best HW Emulator in market. To understand more on what we do, you can visit Palladium website. Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world. Job Description: Development of Firmware for a highly parallel distributed system. Development, Testing, validation, deployment, debugging of Firmware of Palladium Emulation system. You will be part of Research and Development (R&D) to build, maintain our next generation Emulation system. Customer support and Creation of tools for debugging system failures is also part of job. Requirements: Complete Computer Engineering or Bachelor’s in computer science/Computer Engineering with 2+ years’ experience in relevant field.. Knowledge and experience with Object-oriented programming. Knowledge on advanced data structures and algorithms (graph algorithm + basics). Knowledge of C++/Python programming language. Knowledge of Linux Operating System. Knowledge with Unix environment management. Very good spoken and written English and Portuguese. Nice to have: Master with Computer Science is a plus. Experience developing software using Perforce version control systems. Experience with scripting environments - Tcl and Python. Knowledge/Experience with simulation and/or emulation. Knowledge/Experience EDA and VLSI design, including Verilog and VHDL languages. Knowledge of Linux Kernel, Kernel drivers, Linux setup, Linux build. Knowledge of Agentic AI. Knowledge of Ethernet, InfiniBand and/or RoCE. Additional Job Details: Employment category: CLT Employment term: 40 hours/week. Competitive benefits. Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil. About Cadence Design Systems: Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com . We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is seeking a HPC Server Farm Engineer to join our team to support, manage, and improve the DevOps environment. The candidate should have hands-on experience with cloud solutions and proven expertise in working directly with R&D software development teams to develop solutions to optimize their working environment collaboratively. Cadence has a 30-year history of applying leading-edge optimization and analysis algorithms to highly complex problems in semiconductor and electronic design, verification, and analysis. Each day with Cadence offers exciting opportunities to create a better, more connected world. We are leading the charge to solve technology’s toughest challenges. Working at Cadence means working alongside the industry’s brightest people and innovating for the biggest, most innovative companies around the globe. Location: San Jose, CA (on-site position) Responsibilities Supporting multiple geological locations to serve user communities across North America, Europe, and Asia sites. Focusing on improving R&D productivity and committing to customer success. Build, deploy, and optimize HPC compute clusters using LSF or Slurm. Automate infrastructure provisioning using Infrastructure as Code (IaC) tools Troubleshoot and resolve issues across development, testing, and production environments Operating, managing, and enhancing the internal compute farm and associated cloud (Azure). Maintaining, enhancing, monitoring, reporting, and improving its efficiency. Requirements 7+ years of technical experience architecting, managing, and improving HPC environments running both Windows and Linux. 3+ years working in a global group, coordinating support, strategies, projects, and operations across multiple geographies in a team-oriented approach Solid understanding and proven operational experience with DevSecOps and best practices Experience building and managing CI/CD pipeline in cloud (Azure preferred) Strong Linux administration skills and problem-solving skills Experience working directly with R&D software development teams to collaboratively develop solutions to optimize their working environment Experience in HPC using LSF or Slurm is preferred. Strong process focus shown through documentation, change management, incident management and problem-resolution activities Education: BS / MS in computer science or related field The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Software Engineer II: Hardware Verification Compiler to work with us in Belo Horizonte, Brazil. At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For . As a Software Engineer II: Hardware Verification Compiler, you will be part of the Palladium Compiler Development team, contributing to Cadence's Palladium Platform in Belo Horizonte, Brazil. The team develops compiler technology for Palladium, a highly scalable emulation system used to verify advanced electronic designs. You will help develop high-performance compiler capabilities for large-scale model checking and structural checking, with opportunities to apply multithreading and distributed computing. Working at Cadence is dynamic, fast paced, and integrated with other teams all around the world. Job Description: Contribute to the development of compiler technology for the Cadence Palladium Platform. Design and implement scalable software solutions for large compile workloads, including model checking and structural checking. Apply creativity and strong problem-solving skills to improve compiler functionality, scalability, and performance. Learn and apply multithreading and distributed-computing techniques to solve large-scale compilation problems. Develop, debug, test, and maintain production-quality C/C++ software in a Linux/Unix environment. Collaborate with local and global engineering teams on design, implementation, validation, and issue resolution. Requirements: Complete Bachelor's degree or MS in engineering, computer science or related field. Professional experience and strong understanding of data structures, algorithms and databases. Demonstrated proficiency in C++, gdb debugging, and general software development skills Familiarity with Linux/Unix development. Exposure to build and version-control systems. Coursework in Hardware Descript Language, such as Verilog, SystemVerilog, VHDL. Exposure to electronic design platforms. Great communication in English and Portuguese. Additional Job Details: Employment category: CLT Employment term: 40 hours/week. Competitive benefits. Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil. About Cadence Design Systems : Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com. The Cadence Palladium Platform is world most scalable emulation system that verifies most of the latest design innovations in electronics worldwide. We are looking for a talented engineer to join our team and contribute to the world’s fastest emulator compiler development. You’ll have a great opportunity to make a difference by applying your creativity and problem-solving skills, learn and/or apply multi-threading/distributed computing to solve large scale compile problems such model checking and structural checking to ensure functionality. We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Title Principle Application Engineer – Customer Excellence Department Customer Success / Customer Excellence Reporting To Head of Customer Success Location Remote / Hybrid Travel Periodic travel to customer sites, industry events, and internal planning sessions POSITION OVERVIEW The Customer Excellence Manager (CEM) is responsible for helping strategic customers achieve measurable business and engineering outcomes through successful adoption of our simulation and engineering software solutions. The CEM serves as the trusted advisor and primary post-sales relationship owner, developing customer success plans, driving adoption initiatives, monitoring customer health and sentiment, and ensuring customers realize maximum value from their investment. The ideal candidate combines strong CAE and engineering software knowledge with customer engagement, strategic account management, stakeholder alignment, and business acumen. This role requires close collaboration with Sales, Application Engineering, Support, Product Management, and Marketing teams to deliver exceptional customer outcomes while supporting retention and long-term account growth. Key Responsibilities Customer Success & Value Realization: Own customer success outcomes by driving product adoption, value realization, and achievement of customer business and engineering objectives throughout the customer lifecycle. Strategic Customer Engagement: Build trusted relationships with technical, management, and executive stakeholders, serving as a strategic advisor and advocate for customer success. Customer Health & Retention: Monitor customer health, adoption trends, and sentiment to proactively identify risks, develop recovery plans, and support long-term customer retention. Account Planning & Growth: Collaborate with Sales and Account Teams to contribute customer insights, support account planning activities, and identify opportunities for product adoption, expansion, and growth. Cross-Functional Leadership: Coordinate activities across Sales, Application Engineering, Support, Product Management, Professional Services, and Marketing to ensure successful customer outcomes. Voice of the Customer: Represent customer needs and feedback within the organization, helping influence product priorities, adoption strategies, and customer experience improvements. Executive Business Reviews & Governance: Lead customer governance discussions and business reviews that demonstrate value, align stakeholders, identify opportunities, and strengthen strategic relationships. Customer Advocacy: Develop customer champions and advocates who can participate in reference programs, industry events, case studies, and other strategic engagement initiatives. Qualifications Education Bachelor's or Master's degree in Mechanical Engineering, Aerospace Engineering, Automotive Engineering, Industrial Engineering, or a related engineering discipline. Experience 5+ years of experience in Customer Success, Technical Account Management, Business Development, Application Engineering, Technical Consulting, Pre-Sales, or Account Management within engineering software, CAE, simulation, PLM, CAD, or related technology industries. Experience managing strategic customer relationships and driving long-term adoption programs. Experience conducting customer reviews, executive engagements, and technical discussions with multiple stakeholder levels. Proven history of supporting customer retention, adoption growth, and business expansion initiatives. Core Competencies Strong customer-centric mindset. Strategic account planning and stakeholder management. Ability to leverage AI tools to enhance customer engagement, adoption, reporting, and productivity. Executive communication and presentation skills. Customer health and sentiment management. Value realization and adoption planning. Cross-functional leadership and influence without authority. Analytical and problem-solving capabilities. Strong business and commercial acumen. Ability to manage multiple priorities in a fast-paced environment. Tools & Platforms CRM platforms such as Salesforce. Customer Success platforms such as Gainsight. Bring AI expertise Customer adoption and engagement analytics tools. Microsoft Office and collaboration platforms. Key Performance Indicators (KPIs) Customer Outcomes: Achievement of customer success plan objectives; customer adoption and utilization growth; successful onboarding and adoption milestones. Customer Health: Customer health score improvements; customer sentiment and relationship strength; risk identification and mitigation effectiveness. Retention & Growth: Customer retention rate; contribution to Net Revenue Retention (NRR); expansion opportunities identified and supported; renewal readiness and account stability. Customer Advocacy: Customer references and success stories generated; product feedback submitted and acted upon; participation in advocacy and community initiatives. Operational & Reporting: Accurate customer planning, reporting, and cross-functional execution. Ideal Candidate Profile A successful candidate will be a technically credible CAE professional who can build trusted relationships, drive customer adoption, influence cross-functional teams, manage customer sentiment, contribute to account planning, and identify business growth opportunities while ensuring customers achieve measurable engineering and business outcomes. We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join the team behind Xcelium , the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning. We are looking for experienced C++ software engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon. Responsibilities: Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features. Enhance and support Timing Constraints Verification technology used inside Xcelium simulator. The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs. Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint. Lead junior engineers and collaborate with global team members to deliver high-quality results in a distributed environment. Contribute to technical discussions, code reviews, and process improvements. Write Specifications and Unit Tests for your code. Position Requirements/Qualifications: MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience OR PhD with a minimum of 10 years of experience 10+ years of experience in EDA software development. Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool. Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog. Experience in multi-threaded/ concurrent programming. Ability to quickly learn new technologies and adapt to project requirements. Prior experience with RTL/logic simulation software development is an added plus. The annual salary range for California is $210,000 to $390,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join the team behind Xcelium , the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning. We are looking for an experienced C/C++ software engineer to join the Xcelium Software Development Team to develop and enhance RTL/logic simulation products. Responsibilities: Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features. Enhance and support Timing Constraints Verification technology used inside Xcelium simulator. The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs. Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint. Collaborate with global team members to deliver high-quality results in a distributed environment. Write Specifications and Unit Tests for your code. Position Requirements/Qualifications: MS/PhD in Computer Science or Electrical Engineering. MS in Computer Science or Electrical Engineering with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience 5+ years of experience in EDA software development. Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool. Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog. Experience in multi-threaded/ concurrent programming. Ability to quickly learn new technologies and adapt to project requirements. Prior experience with RTL/logic simulation software development is an added plus. The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.